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this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtron?s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 3.4 may 2009 page 1 of 14 fm25cl64 64kb serial 3v f-ram memory features 64k bit ferroelectric nonvolatile ram ? organized as 8,192 x 8 bits ? unlimited read/write cycles ? 45 year data retention ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface - spi ? up to 20 mhz frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software protection low power consumption ? low voltage operation 2.7-3.65v ? 1 a standby current industry standard configuration ? industrial temperature -40 c to +85 c ? 8-pin ?green?/rohs soic and tdfn packages ? grade 3 aec-q100 qualified (soic only) description the fm25cl64 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. unlike serial eeproms, the fm25cl64 performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte has been transferred to the device. the next bus cycle may commence without the need for data polling. in addition, the product offers virtually unlimited write endurance, orders of magnitude more endurance than eeprom. f-ram also exhibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. these capabilities make the fm25cl64 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm25cl64 provides substantial benefits to users of serial eeprom as a hardware drop-in replacement. the fm25cl64 uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. device specifications are guaranteed over an industrial temperature range of -40c to +85c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage vss ground ordering information fm25cl64-g ? ?green? 8-pin soic fm25cl64-gtr ? ?green? 8-pin soic, tape & reel fm25cl64-dg ?green? 8-pin tdfn FM25CL64-DGTR ?green? 8-pin tdfn, tape & reel fm25cl64-s * 8-pin soic fm25cl64-str * 8-pin soic, tape & reel ? grade 3 aec-q100 qualified * end of life. last time buy june 2009. /cs so /wp vss vdd /hold sck si 8 7 6 5 1 2 3 4 top view cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25cl64 rev. 3.4 may 2009 page 2 of 14 instruction decode clock generator control logic write protect instruction register address register counter 2,048 x 32 fram array 13 data i/o register 8 nonvolatile status register 3 wp cs hold sck so si figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op-code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the status register. this is critical since other write protection features are controlled through the status register. a complete explanation of write protection is provided below. *note that the function of /wp is different from the fm25040 where it prevents all writes to the part. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be connected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri- stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply (2.7v to 3.65v) vss supply ground
fm25cl64 rev. 3.4 may 2009 page 3 of 14 overview the fm25cl64 is a serial f-ram memory. the memory array is logically organized as 8,192 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f-ram is similar to serial eeproms. the major difference between the fm25cl64 and a serial eeprom with the same pinout is the f-ram?s superior write performance. memory architecture when accessing the fm25cl64, the user addresses 8,192 locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. the upper 3 bits of the address range are ?don?t care? values. the complete address of 13-bits specifies each byte address uniquely. most functions of the fm25cl64 either are controlled by the spi interface or are handled automatically by on-board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm25cl64 due to its fast write cycle and high endurance as compared with eeprom. in addition there are less obvious benefits as well. for example in a high noise environment, the fast-write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note: the fm25cl64 contains no power management circuits other than a simple internal power-on reset circuit. it is the user?s responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip enable active. serial peripheral interface ? spi bus the fm25cl64 employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high-speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25cl64 operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data-in, data-out, and chip select. a typical system configuration uses one or more fm25cl64 devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data-in, and data-out pins are common among all devices. the chip select and hold pins must be driven separately for each fm25cl64 device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the /hold pin. figure 3 shows a configuration that uses only three pins. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm25cl64 will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25cl64 supports modes 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm25cl64 on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op-codes. these op-codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op-code. following the op-code, any addresses and data are then transferred. note that the wren and wrdi op-codes are commands with no subsequent data transfer. important: the /cs pin must go inactive after an operation is complete and before a new op-code can be issued. there is one valid op-code only per active chip select.
fm25cl64 rev. 3.4 may 2009 page 4 of 14 spi microcontroller fm25cl64 so si sck cs hold fm25cl64 so si sck cs hold sck mosi miso ss1 ss2 hold1 hold2 mosi : master out slave in miso : master in slave out ss : slave select figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 0 1 2 3 4 5 6 7 spi mode 3: cpol=1, cpha=1 0 1 2 3 4 5 6 7 figure 4. spi modes 0 & 3
fm25cl64 rev. 3.4 may 2009 page 5 of 14 data transfer all data transfers to and from the fm25cl64 occur in 8-bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of sck. outputs are driven from the falling edge of sck. command structure there are six commands called op-codes that can be issued by the bus master to the fm25cl64. they are listed in the table below. these op-codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op-code commands name description op-code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b wren - set write enable latch the fm25cl64 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op-code will allow the user to issue subsequent op-codes for write operations. these include writing the status register (wrsr) and writing the memory (write). sending the wren op-code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit ? only the wren op-code can set this bit. the wel bit will be automatically cleared on the rising edge of /s following a wrdi, a wrsr, or a write operation. this prevents further writes to the status register or the f-ram array without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
fm25cl64 rev. 3.4 may 2009 page 6 of 14 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op- code, the fm25cl64 will return one byte with the contents of the status register. the status register is described in detail in a later section. wrsr ? write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm25cl64, /wp only prevents writing to the status register, not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. figure 7. rdsr bus configuration figure 8. wrsr bus configuration (wren not shown) status register & write protection the write protection features of the fm25cl64 are multi-tiered. first, a wren op-code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the status register. as described above, writes to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4-6 are fixed at 0 and cannot be modified. note that bit 0 (?ready? in eeproms) is unnecessary as the f-ram writes in real-time and is never busy. the wpen, bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write- protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper ?) 1 0 1000h to 1fffh (upper ?) 1 1 0000h to 1fffh (all)
fm25cl64 rev. 3.4 may 2009 page 7 of 14 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register. thus the status register is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f-ram technology. unlike spi-bus eeproms, the fm25cl64 can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory begin with a wren op- code with /cs being asserted and deasserted. the next op-code is write. the write op-code is followed by a two-byte address value. the upper 3- bits of the address are ignored. in total, the 13-bits specify the address of the first data byte of the write operation. this is the starting address of the first data byte of the write operation. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps /cs low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is written msb first. the rising edge of /cs terminates a write operation. a write operation is shown in figure 9. eeproms use page buffers to increase their write throughput. this compensates for the technology?s inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the 8 th clock). this allows any number of bytes to be written without page buffer delays. read operation after the falling edge of /cs, the bus master can issue a read op-code. following the read command is a two-byte address value. the upper 3-bits of the address are ignored. in total, the 13-bits specify the address of the first byte of the read operation. this is the starting address of the first byte of the read operation. after the op-code and address are issued, the device drives out the read data on the next 8 clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and /cs is low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read operation. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
fm25cl64 rev. 3.4 may 2009 page 8 of 14 0 1 2 34567 0 1 2 345 34567 0 1 2 34567 op-code 0 0 0 0 0 0 1 0 msb 13-bit address xxx121110 4321076543210 lsb msb lsb cs sck si so data figure 9. memory write (wren not shown) 0 1 2 34567 0 1 2 345 34567 0 1 2 34567 op-code 0 0 0 0 0 0 1 msb 13-bit address xxx121110 43210 76543210 lsb msb lsb cs sck si so data 1 figure 10. memory read
fm25cl64 rev. 3.4 may 2009 page 9 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any pin with respect to v ss -1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - machine model (jedec std jesd22-a115-a) 4kv 300v package moisture sensitivity level msl-1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to + 85 c, v dd = 2.7v to 3.65v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.7 3.3 3.65 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 20.0 mhz - - 0.35 7 ma ma 1 i sb standby current - 1 1 1 notes 1. sck toggling between v dd -0.3v and v ss , other inputs v ss or v dd -0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss v in v dd and v ss v out v dd . 4. characterized but not 100% tested in production. applies only to /cs and sck pins.
fm25cl64 rev. 3.4 may 2009 page 10 of 14 ac parameters (t a = -40 c to + 85 c, c l = 30pf) v dd 2.7 to 3.0v v dd 3.0 to 3.65v symbol parameter min max min max units notes f ck sck clock frequency 0 18 0 20 mhz t ch clock high time 25 22 ns 1 t cl clock low time 25 22 ns 1 t csu chip select setup 10 10 ns t csh chip select hold 10 10 ns t od output disable time 20 20 ns 2 t odv output data valid time 25 20 ns t oh output hold time 0 0 ns t d deselect time 60 60 ns t r data in rise time 50 50 ns 2,3 t f data in fall time 50 50 ns 2,3 t su data setup time 5 5 ns t h data hold time 5 5 ns t hs /hold setup time 10 10 ns t hh /hold hold time 10 10 ns t hz /hold low to hi-z 20 20 ns 2 t lz /hold high to data active 20 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. characterized but not 100% tested in production. 3. rise and fall times measured between 10% and 90% of waveform. capacitance (t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output capacitance (so) - 8 pf 1 c i input capacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. ac test conditions input pulse levels 10% and 90% of v dd input rise and fall times 5 ns input and output timing levels 0.5 v dd output load capacitance 30 pf
fm25cl64 rev. 3.4 may 2009 page 11 of 14 serial data bus timing 1/fck tcl tch tcsh todv toh tod tcsu tsu th td tr tf /hold timing data retention (v dd = 2.7v to 3.65v, +85c) parameter min max units notes data retention 45 - years
fm25cl64 rev. 3.4 may 2009 page 12 of 14 mechanical drawings 8-pin soic (jedec ms-012 variation aa) pin 1 3.90 0.10 6.00 0.20 4.90 0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45 0.40 1.27 0.19 0.25 0 - 8 recommended pcb footprint 7.70 0.65 1.27 2.00 3.70 refer to jedec ms-012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxx= part number, p= package type, t= temperature (a=automotive, blank=ind.) lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm25cl64, ?green? soic package, year 2006, work week 29 fm25cl64g a60013g1 ric0629 xxxxxx-pt lllllll ricyyww
fm25cl64 rev. 3.4 may 2009 page 13 of 14 8-pin tdfn (4.0mm x 4.5mm body, 0.95mm pitch) pin 1 4.00 0.1 4.50 0.1 0.75 0.05 0.40 0.05 0.95 0.20 ref. pin 1 id 0.0 - 0.05 2.85 ref 3.60 0.10 2.60 0.10 exposed metal pad. do not connect to anything except vss. 0.30 0.1 4.30 0.50 0.95 recommended pcb footprint 0.50 2.70 3.70 note: all dimensions in millimeters . tdfn package marking scheme for body size 4.0mm x 4.5mm legend: r=ramtron, g=?green?/rohs tdfn package, xxxx=base part number llll= lot code, yy=year, ww=work week example: ?green? tdfn package, fm25cl64, lot 0013, year 2006, work week 29 rg5l64 0013 0629 rgxxxx llll yyww
fm25cl64 rev. 3.4 may 2009 page 14 of 14 revision history revision date summary 0.0 5/10/01 initial release 0.1 7/5/01 updated ac and dc specifications. changed ac test conditions and load circuit. 0.2 10/11/01 added unlimited endurance bullet. changed data retention table. 0.3 1/8/02 changed operating vdd voltage range to 3.0 ? 3.65v. reduced idd supply current limits. 2.0 2/19/03 updated to production status. added note to output data valid spec. 2.1 4/22/03 changed operating vdd voltage range to 2.7 ? 3.65v with separate ac timing specs defined below 3.0v operation. reduced input leakage spec. 2.2 3/17/04 added ?green? package. updated package mechanical drawing. 3.0 9/3/04 added dfn packaging option. added dfn mechanical drawing. new rev. number to comply with updated scheme. 3.1 3/9/05 improved data retention spec to 45 years. removed ?preliminary? from dfn package drawing. added note about powering down with /cs active (pg 3). added esd and package msl ratings. 3.2 7/19/05 changed dfn name to tdfn. added tdfn pcb footprint. corrected tdfn package heading from 0.65mm to 0.95mm. 3.3 2/28/08 removed ?s package option. it is not recommended for new designs, use ?g instead. changed/improved i dd spec limits. removed 5mhz i dd entry. changed tdfn package marking scheme. 3.31 6/3/2008 removed sentence referencing table 4 from write operation paragraph (p. 7). 3.4 5/26/2009 added tape and reel ordering information. added note that soic device is grade 3 aec-q100 qualified. added last time buy notice on ?s ordering numbers.

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